library ieee;

use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

use work.cpu_utils.all;

entity mux_2 is
	generic ( 
		size: integer := 32;
		Tpd : Time := unit_delay);
	port (
			in_0, in_1 : in bit_vector(size-1 downto 0);
			y : out bit_vector(size-1 downto 0);
			sel : in bit);
end mux_2;

architecture mux_2_arh of mux_2 is
begin
	with sel select
		y <= in_0 after Tpd when '0',
		in_1 after Tpd when '1';
end mux_2_arh;